1. Field of the Invention
The present invention relates to digital computing, and more particularly to mechanisms and techniques to detect when the logic within a processor has completed.
2. Description of the Related Art
The frequency of a processor CPU clock signal is an important factor in evaluating the overall performance of a computer system. In general, as the speed of the processor clock signal increases, the time required to execute various instructions decreases. The speed of the clock signal is limited by several factors. These factors include temperature, process variation, and voltage skew, and may include many other conditions. In typical synchronous designs, manufacturers of logic chips usually provide a maximum clock frequency that is guaranteed to operate properly under worst-case conditions. The system designer then must ensure that the system designed around that particular logic chip xe2x80x9cmeetsxe2x80x9d the worst-case specification. This worst-case clock rate provides degraded performance at any time that the processor is running under better than worst-case conditions. Often-times the system is designed to not only meet the worst-case specification but to operate under very favorable conditions and therefore is capable of operating at a higher clock rate in those conditions. Conversely, if a designer wants to design a system that operates in a harsh environment, she generally cannot get a logic chip that is specified to operate properly in that environment. What is desired is an apparatus and method for dynamically altering the clock rate of a processor to allow for maximum performance under varying conditions.
The prior art discloses inventions for dynamically altering the clock rate of a processor. U.S. Pat. No. 5,490,059, issued to Mahalingaiah et al, and U.S. Pat. No. 5,451,892 issued to Bailey, both disclose inventions that use the temperature of the semiconductor die in determining the frequency of a timing signal to be applied to a processor clock. These inventions are motivated by a desire to operate a logic chip at a speed that need not account for thermal margins. When a logic chip is sold by a manufacturer, it is usually guaranteed to operate at or below a specified temperature. Since the manufacturer does not usually control the choice of the enclosure that the logic chip will be installed in, or what climate the resulting system will be used in, the logic chip is clocked at a rate where it can function in a worst-case environment. It is usually necessary for the manufacturer, when specifying the maximum temperature, to assume that the enclosure will have little ventilation. It is also usually necessary for the manufacturer to assume that the part will be used in an environment where the air temperature is 40xc2x0 C.xe2x80x94an uncommon occurrence.
The prior art presents serious shortcomings. One such shortcoming is the inherent inaccuracy of on-die thermal sensors because these sensors are subject to process variations. These process variations present the undesirable requirement that the computer containing a prior art device be calibrated.
Another shortcoming of the prior art is that the most demanding applications will run slower on prior art systems than less demanding applications will. The function being performed by a chip affects its operating speed under the prior art systems because the chip itself generates heat. The difference between the allowed temperature and the actual temperature of the surrounding air determines the rate at which such heat dissipates. In circumstances when a demanding application is being run on a system with the prior art device in an environment approaching the maximum heat specification, the heat generated by the chip can cause the clock to slow. For instance, when running a computer game that involves a relatively large number of floating point calculations, more of the circuits in a traditionally designed computer will be switching and therefore generating relatively more heat than simpler applications. Such a situation is more likely to cause the prior art chips to exceed their thermal limits and therefore slow their clocks. The result is undesirable from a user""s point of view, in that his most demanding applications will run slower than his less demanding ones. The present invention overcomes these drawbacks of the prior art.
The apparatus and method of the present invention help to overcome, in large part, the reduced efficiency problems associated with a predetermined clock rate that will guarantee satisfactory performance under worst-case conditions. That is, the present invention detects when a processor""s logic has completed within a given clock cycle. This information can be useful in determining when a processor is operating under conditions that are better than the worst-case situation, so that adjustments may be made to allow a processor to work at a higher clock rate. A system using the present invention directly measures signal speed and requires less margin than the prior art systems that adjust clock rate based on temperature.
The present invention discloses an apparatus and method for determining when a logic circuit has completed within a clock cycle. Such information may be used to dynamically control the frequency of a processor clock. The preferred embodiment utilizes dynamic logic to deliver a critical signal to the transition detection circuit. In the preferred embodiment, the transition detection circuit comprises a static NOR gate. In an alternative embodiment, the transition detection circuit comprises an N-NARY circuit that xe2x80x9cor""sxe2x80x9d all N-WIRES of an N-NARY 1-of-n signal. The transition detection circuit detects that a critical signal has transitioned from the pre-charge state. The output of the transition detection circuit may be fed into a series of delayed flip-flop latches. This allows the present invention to be used in a circuit that determines when the critical signal transitioned from the pre-charge state relative to the clock. Using this information, the present invention may be used by a dynamic clock adjustment circuit to vary the speed of the clock.